View BR24A01AFJ-WM_4692796.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

BR24A01AFJ-WM 1/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. serial eeprom series high reliability series eeproms i2c bus br24a -wm series description br24a -wm series is a serial eeprom of i 2 c bus interface method. features 1) completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock(scl) and serial data(sda) 2) other devices than eeprom can be connected to the same port, saving microcontroller port 3) 2.5v~5.5v single power source action most suitable for battery use 4) page write mode useful for initia l value write at factory shipment 5) highly reliable connection by au pad and au wire 6) auto erase and auto en d function at data rewrite 7) low current consumption at write operation (5v) : 1.2ma (typ.) *1 at read operation (5v) : 0.2ma (typ.) at standby operation (5v) : 0.1 a (typ.) 8) write mistake prevention function write (write protect) function added write mistake prevention function at low voltage 9) sop8/sop-j8/msop8 compact package *2 10) data rewrite up to 100,000 times 11) data kept for 40 years 12) noise filter built in scl / sda terminal 13) shipment data all address ffh *1 br24a32-wm,br24a64-wm : 1.5ma *2 refer to following list page write number of pages 8byte 16byte 32byte product number br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm br24a series capacity bit format type power source voltage sop8 sop-j8 msop8 1kbit 1288 br24a01a-wm 2.5 5.5v 2kbit 2568 br24a02-wm 2.5 5.5v 4kbit 5128 br24a04-wm 2.5 5.5v 8kbit 1k8 br24a08-wm 2.5 5.5v 16kbit 2k8 br24a16-wm 2.5 5.5v 32kbit 4k8 br24a32-wm 2.5 5.5v 64kbit 8k8 br24a64-wm 2.5 5.5v no.09001ect02
br24a -wm series technical note 2/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. absolute maximum ratings (ta=25 ) parameter symbol limits unit impressed voltage vcc -0.3 +6.5 v permissible dissipation pd 450 (sop8) *1 mw 450 (sop-j8) *2 310 (msop8) *3 storage temperature range tstg -65 +125 action temperature range topr -40 +105 terminal voltage - -0.3 vcc+1.0 v when using at ta=25 or higher, 4.5mw(*1,*2) , 3.1mw(*3) to be reduced per 1 memory cell characteristics (vcc=2.5 5.5v) parameter limits unit test condition min. typ. max. number of data rewrite times *1 100,000 - - times ta=-40 105 data hold years *1 40 - - years ta=25 shipment data all address ffh *1 not 100% tested recommended operating conditions parameter symbol limits unit power source voltage vcc 2.5 5.5 v input voltage v in 0 vcc electrical characteristics (unl ess otherwise specified, ta=-40 +105 , vcc=2.5 5.5v) parameter symbol limits unit conditions min. typ. max. ?high? input voltage v ih 0.7vcc - - v ?low? input voltage v il - - 0.3 vcc v ?low? output voltage 1 v ol - - 0.4 v i ol =3.0ma (sda) input leak current i li -1 - 1 a v in =0v vcc output leak current i lo -1 - 1 a v out =0v vcc, (sda) current consumption at action i cc1 - - 2.0 *1 ma vcc=5.5v,f scl =400khz, t wr =5ms, byte write, page write 3.0 *2 i cc2 - - 0.5 ma vcc=5.5v,f scl =400khz random read, current read, sequential read standby current i sb - - 2.0 a vcc=5.5v, sda ? scl=vcc a0, a1, a2=gnd, wp=gnd radiation resistance design is not made. *1 br24a01a/02/04/08/16-wm, *2 br24a32/64-wm action timing characteristics (unless otherwise specified, ta= - 40 +105 , vcc=2.5 5.5v) parameter symbol fast-mode 2.5v Q vcc Q 5.5v standard-mode 2.5v Q vcc Q 5.5v unit min. typ. max. min. typ. max. scl frequency f scl - - 400 - - 100 khz data clock ?high? time t high 0.6 - - 4.0 - - s data clock ?low? time t low 1.2 - - 4.7 - - s sda, scl rise time *1 t r - - 0.3 - - 1.0 s sda, scl fall time *1 tf - - 0.3 - - 0.3 s start condition hold time t hd:sta 0.6 - - 4.0 - - s start condition setup time t su:sta 0.6 - - 4.7 - - s input data hold time t hd:dat 0 - - 0 - - ns input data setup time t su:dat 100 - - 250 - - ns output data delay time t pd 0.1 - 0.9 0.2 - 3.5 s output data hold time t dh 0.1 - - 0.2 - - s stop condition setup time t su:sto 0.6 - - 4.7 - - s bus release time before transfer start tb uf 1.2 - - 4.7 - - s internal write cycle time t wr - - 5 - - 5 ms noise removal valid period (sda, scl terminal) ti - - 0.1 - - 0.1 s wp hold time t hd:wp 0 - - 0 - - ns wp setup time t su:wp 0.1 - - 0.1 - - s wp valid time t high:wp 1.0 - - 1.0 - - s *1 not 100% tested
br24a -wm series technical note 3/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. fast-mode and standard-mode fast-mode and standard-mode are of same actions, and mode is changed. they are distinguished by action speeds. 100khz action is called standard-mode, and 400khz action is called fast-mode. this action frequency is the maximum action frequency, so 100khz clock may be used in fast-mode. at vcc=2.5v 5.5v , 400khz, namely, action is made in fastmode. (action is made also in standard-mode.) sync data input / output timing input read at the rise edge of scl data output in sync with the fall of scl fig.1-(a) sync data input / output timi ng fig.1-(b) start-stop bit timing fig.1-(c) write cycle timing fig.1-(d) wp timing at write execution at write execution, in the area from the d0 taken clock rise of the first data(1), to twr, set wp=?low?. by setting wp ?high? in the area, write can be cancelled. when it is set wp=?high? during tw r, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. fig.1-(e) wp timing at write cancel sda tsu:sta tsu:sto thd:sta start bit stop bit scl thigh:wp wp sda d1 d0 ack ack data(1) data(n) twr scl sda write data ( n-th address ) stop condition start condition scl wr ack d0 sd a () sda () thd:sta thd:dat tsu:dat tbuf tpd tdh tlow thigh tr tf scl (input) (output) scl sda wp hd wp ???? wr d1 d0 a ck a ck data(1) data(n) tsu wp stop condition
br24a -wm series technical note 4/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. block diagram fig.2 block diagram pin assignment and description terminal name input / output function br24a01a-wm br24a02-wm br24a04-wm br24a 08-wm br24a16-wm br24a32-wm br24a64-wm a0 input slave address setting not connected slave address setting a1 input slave address setting not connected slave address setting a2 input slave address setting not used slave address setting gnd - reference voltage of all input / output, 0v sda input / output slave and word address, serial data input serial data output scl input serial clock input wp input write protect terminal vcc - connect the power source. 1kbit~64kbit eeprom arra y control circuit high voltage generating circuit power source voltage detection 7bit 8bit 9bit 10bi t 11bit 12bit 13b it address decoder slave - word address register data register 8bit 7bit 8bit 9bit 10bi t 11bit 12bit 13b it start stop ack *1 *1 1 2 3 4 8 7 6 5 sda scl wp vcc a1 a0 a2 gnd *2 *2 *2 1 7bit : br24a01a-wm 8bit : br24a02-wm 9bit : br24a04-wm 10bit : br24a08-wm 11bit : br24a16-wm 12bit : br24a32-wm 13bit : br24a64-wm 2 a0=n.c. : br24a04-wm a0, a1=n.c. : br24a08-wm a0, a1= n.c. a2=don?t use : br24a16-wm 1 2 3 4 8 6 5 br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm a0 7 a1 a2 gnd vcc wp scl sda
br24a -wm series technical note 5/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] icc2[ma] fscl=400khz data=aah ta=25 ta=-40 ta=105 spec 0 0.2 0.4 0.6 0.8 1 1.2 0123456 vcc[v] ili[a] ta=105 ta=25 ta=-40 spec 0 1 2 3 4 5 6 0123456 vcc[v] vih1,2[v] ta=105 ta=-40 ta=25 spec 0 1 2 3 4 5 6 0123456 vcc[v] vil1,2[v] ta=105 ta=-40 ta=25 spec fig.3 h input voltage vih1,2(scl,sda,wp) fig.4 l input voltagev il1,2(scl,sda,wp) 0 0.2 0.4 0.6 0.8 1 0123456 iol1[ma] vol1[v] ta=25 ta=-40 ta=105 spec 0 0.2 0.4 0.6 0.8 1 1.2 0123456 vcc[v] ilo[a] spec ta=105 ta=25 ta=-40 fig.5 l output voltagevol1-iol1(vcc=2.5v) fig.6 input leak current ili(scl,wp) fig.7 output leak current ilo(sda) 0 0.5 1 1.5 2 2.5 0123456 vcc[v] icc1[ma] fscl=400khz data=aah ta=25 ta=105 ta=-40 spec [br24a01/02/04/08/16 series] 0 0.5 1 1.5 2 2.5 3 3.5 0123456 vcc[v] icc1[ma] spec ta=25 ta=105 ta=-40 fscl=100khz data=aah [br24a32/64 series] 0 0.5 1 1.5 2 2.5 0123456 vcc[v] isb[a] ta=-40 ta=105 ta=25 spec 1 10 100 1000 10000 0123456 vcc[v] fscl[khz] ta=105 ta=25 ta=-40 spec2 spec1 0 1 2 3 4 5 0123456 vcc[v] thigh [s] spec2 ta=-40 ta=25 ta=105 spec1 0 1 2 3 4 5 0123456 vcc[v] tlow[s] spec2 spec1 ta=105 ta=25 ta=-40 0 1 2 3 4 5 0123456 vcc[v] thd:sta[s] spec2 spec1 ta=105 ta=25 ta=-40 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] icc2[ma] spec fscl=100khz data=aah ta=-40 ta=105 ta=25 fig.9 current consumption at write action icc1 (fscl=400khz) fig.10 current consumption at read action icc2 (fscl=400khz) fig.12 current consumption at write action icc1 (fscl=100khz) fig.13 current consumption at read action icc2 (fscl=100khz) fig.14 standby currentisb fig.15 scl frequencyfscl fig.16 data clock "h" time thigh fig.17 data clock "l" time tlow fig.18 start condition hold timethd:sta 0 1 2 3 4 5 6 0123456 vcc[v] tsu:sta[s] spec2 spec1 ta=-40 ta=25 ta=105 -200 -150 -100 -50 0 50 0123456 vcc[v] thd:dat(high)[ns] spec1,2 ta=-40 ta=25 ta=105 fig.19 start condition setup time tsu:sta fig.20 input data hold time thd:dat(high) 0 0.5 1 1.5 2 2.5 3 3.5 0123456 vcc[v] icc1[ma] fscl=400khz data=aah ta=25 ta=105 ta=-40 spec [br24a32/64 series] fig.8 current consumption at write action icc1 (fscl=400khz) 0 0.5 1 1.5 2 2.5 0123456 vcc[v] icc1[ma] spec ta=25 ta=105 ta=-40 fscl=100khz data=aah [br24a01/02/04/08/16 series] fig.11 current consumption at write action icc1 (fscl=100khz)
br24a -wm series technical note 6/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(sda h)[s] spec1,2 ta=25 ta=-40 ta=105 0 1 2 3 4 0123456 vcc[v] tpd1[s] spec1 spec2 spec2 ta=-40 ta=25 ta=105 spec1 0 1 2 3 4 0123456 vcc[v] tpd0[s] ta=105 ta=25 ta=-40 spec2 spec1 spec2 spec1 -200 -150 -100 -50 0 50 0123456 vcc[v] thd:dat(low)[ns] spec1,2 ta=-40 ta=105 ta=25 -200 -100 0 100 200 300 0123456 vcc[v] tsu:dat(low)[ns] ta=-40 ta=105 ta=25 spec1 spec2 -200 -100 0 100 200 300 0123456 vcc[v] tsu:dat(high)[ns] ta=105 ta=25 ta=-40 spec1 spec2 fig.21 input data hold timethd:dat(low) fig.22 input data setup timetsu:dat(high) fig.23 input data setup time tsu:dat(low) fig.24 output data delay time tpd0 fig.25 output data delay time tpd1 0 1 2 3 4 5 0123456 vcc[v] tbuf[s] spec2 spec1 ta=-40 ta=25 ta=105 0 1 2 3 4 5 6 0123456 vcc[v] twr[ms] spec1,2 ta=25 ta=-40 ta=105 fig.26 bus release time before transfer start tbuf fig.27 internal write cycle timetwr 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(scl h)[s] spec1,2 ta=-40 ta=25 ta=105 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(scl l)[s] ta=-40 ta=25 ta=105 spec1 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(sda l)[s] spec1 ta=-40 ta=105 ta=25 -0.6 -0.4 -0.2 0 0.2 0123456 vcc[v] tsu:wp[s] spec1,2 ta=105 ta=-40 ta=25 0 0.2 0.4 0.6 0.8 1 1.2 0123456 vcc[v] thigh:wp[s] spec1,2 ta=-40 ta=25 ta=105 fig.28 noise removal valid time ti(scl h) fig.29 noise removal valid time ti(scl l) fig.30 noise removal valid time ti(sda h) fig.31 noise removal v alid time ti(sda l) fig.32 wp setup timetsu:wp fig.33 wp valid timethigh:wp
br24a -wm series technical note 7/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and en ds by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices connected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are ?master? that generates clock and control communicati on start and end, and ?slave? that is controlled by address peculiar to devices. eeprom becomes ?slave?. and the device th at outputs data to bus during data communication is called ?transmitter?, and the dev ice that receives data is called ?receiver?. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start condition (start bit) or not, therefore, unless this confdition is satisfied, any command is executed. stop condition (stop bit recongnition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to sh ow whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write comm and, read command, and this ic at data output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address in put of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low ' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write action outputs acknowledge signal (ack signal) 'l ow', at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detects acknowledge signal (ack signal) 'low'. ? when acknowledge signal (ack signal) is detected, and stop condition is not sent from the master ( -com) side, this ic continues data output. when acknowledge signal (ack si gnal) is not detected, this ic stops data transfer, and recognizes stop cindition (stop bit), and ends read action. and this ic gets in status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? next slave addresses (a2 a1 a0 --- device address) are for se lecting devices, and plural ones can be used on a same bus according to the number of device addresses. ? the most insignificant bit (r/w --- read / write) of slave addr ess is used for designating write or read action, and is as shown below. setting r / w to 0 ------- write (setting 0 to word address setting of random read) setting r / w to 1 ------- read type slave address maximum number of connected buses br24a01a-wm 1 0 1 0 a2 a1 a0 r/w D 8 br24a02-wm 1 0 1 0 a2 a1 a0 r/w D 8 br24a04-wm 1 0 1 0 a2 a1 ps r/w D 4 br24a08-wm 1 0 1 0 a2 p1 p0 r/w D 2 br24a16-wm 1 0 1 0 p2 p1 p0 r/w D 1 br24a32-wm 1 0 1 0 a2 a1 a0 r/w D 8 br24a64-wm 1 0 1 0 a2 a1 a0 r/w D 8 ps, p0 p2 are page select bits. note) up to 4 units br24a04-wm, up to 2 units of br24a08-wm, and one unit of br24a16-wm can be connected. device address is set by 'h' and 'l' of each pin of a0, a1, and a2. fig.34 data transfer timing 1 2 3 4 8 6 5 br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm a0 7 a1 a2 gnd vcc wp scl sda 89 89 89 s p condition condition ack stop ack data data addres s start r/w ack 1-7 sda scl 1-7 1-7
br24a -wm series technical note 8/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. write command write cycle ? arbitrary data is written to eeprom. when to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. the maximum number of write bytes is specified per device of each capacity. up to 32 arbitrar y bytes can be written. (in the case of br24a32 / a64-wm) ? data is written to the address designated by word address (n-th address) ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk : up to 8 bytes ( br24a01a-wm, br24a02-wm : up to 16bytes (br24a04-wm, br24a08-wm,br24a16-wm : up to 32bytes (br24a32-wm, br24a64-wm and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to "internal address increment" of "notes on page write cycle" in p8/16.) ? as for page write cycle of br24a01a-wm and br24a02-wm, after the significant 5 bits (4 significant bits in br24a01a-wm) of word address are designated arbitrarily, and as for page write command of br24a04-wm, br24a08-wm, and br24a16-wm, after page select bit (ps) of sl ave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in br24a01a-wm, and br24a02-wm) is incremented internally, and data up to 16 bytes (up to 8 bytes in br24a01a-wm and br24a02-wm) can be written. ? as for page write cycle of br24a32-wm and br24a64-wm, after the significant 7 bits (in the case of br24a32-wm) of word address, or the significant 8 bits (in the case of br24a64-wm) of word address are designated arbitrarily, by continuing data input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. w r i t e s t a r t r / w a c k s t o p word address(n) dat a (n) sda line a c k a c k data(n+15) a c k slave address 1 0 0 1a0 a1 a2 wa 7 d0 d7 d0 wa 0 note) *1 *2 a1 a2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w s t o p word address data slave address a0 wa 0 d0 a c k sda line a c k a c k note) *1 fig.35 byte write cycle (br24a01a/02/04/08/16-wm) *1 as for wa7, br24a01a-wm becomes don?t care. a1 a2 1 1 0 0 w r i t e s t a r t r / w s t o p 1st word address data slave address a0 d0 a c k sda line a c k a c k note) wa 12 wa 11 * wa 0 a c k 2nd word address d7 *1 * * *1 as for wa12, br24a32-wm becomes don?t care. fig.36 byte write cycle (br24a32/64-wm) *1 as for wa7, br24a01a-wm becomes don?t care. *2 as for br24a01a/02-wm becomes (n+7). fig.37 page write cycle (br24a01a/02/04/08/16-wm) fig.38 page write cycle (br24a32/64-wm) *1 as for wa12, br24a32-wm becomes don?t care. w r i t e s t a r t r / w a c k s t o p 1st w ord address(n) sda line a c k a c k data(n+31) a c k slave address 1 0 0 1a0 a1 a2 d0 note) *1 data(n) d0 d7 a c k 2nd w ord address(n) wa 0 wa 12 wa 11 * * * note) 1 0 0 1a0 a1 a2 *1 *2 *3 fig.39 difference of slave address of each type *1 in br24a16-wm, a2 becomes p2. *2 in br24a08-wm, br24a16-wm, a1 becomes p1. *3 in br24a04-wm, a0 becomes ps, and in br24a08-wm and br24a16-wm, a0 becomes p0.
br24a -wm series technical note 9/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. notes on write cycle continuous input notes on page write cycle list of numbers of page write number of pages 8byte 16byte 32byte product number br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm the above numbers are maximum bytes for respective types. any bytes below these can be written. in the case br24a02-wm, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write. it does not stand 5ms at maximum 8byte=40ms(max.). internal address increment page write mode (in the case of br24a02-wm) for example, when it is started from addres s 06h,therefore, increment is made as below, 06h 07h 00h 01h ---, which please note. *06h ??? 06 in hexadecimal, therefore, 00000110 becomes a binary number. write protect (wp) terminal ? write protect (wp) function when wp terminal is set vcc (h level), data rewrite of all addre sses is prohibited. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this terminal to vcc or gnd, or control it to h level or l level. do not use it open . at extremely low voltage at power on / off, by setti ng the wp terminal 'h', mistake write can be prevented. during twr, set the wp terminal al ways to 'l'. if it is set 'h', write is forcibly terminated. w r i t e s t a r t r / w a c k s t o p word address? data(n) sda line a c k data(n+7) a c k slave address 10 0 1a0 a1 a2 wa 7 d0 d7 d0 *1 a c k note) wa 0 1 1 00 next command twr(maximum : 5ms) command is not accepted for this period. at stop (stop bit), write starts. *2 *3 s t a r t *1 br24a01a-wm becomes don?t care. *2 br24a04-wm, br24a08-w, and br24a16-wm become (n+15). *3 br24a32-wm and br24a64-wm become (n+31). 1 0 0 1a0 a1 a2 *1 *2 *3 fig.42 difference of each type of slave address fig. 40 page write cycle *1 in br24a16-wm, a2 becomes p2. *2 in br24a08-wm, br24a16-wm, a1 becomes p1. *3 in br24a04-wm, a0 becomes ps, and in br24a08-wm and in br24a16-wm, a0 becomes p0. note) wa7 ----- wa4 wa3 wa2 wa1 wa0 0 ----- 0 0 0 0 0 0 ----- 0 0 0 0 1 0 ----- 0 0 0 1 0 0 ----- 0 0 1 1 0 0 ----- 0 0 1 1 1 0 ----- 0 0 0 0 0 --------- --------- --------- 06h significant bit is fixed. no digit up increment
br24a -wm series technical note 10/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal ad dress register without designating address, and is used when to verify just after write cycle. in both the read cycles, sequ ential read cycle is available, and the next address data can be read in succession. ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, and stop condition is not sent from master ( -com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ack signal after d0 and sda signal is started at scl signal 'h' . ? when 'h' is not input to ack signal after d0, s equential read gets in, a nd the next data is output. therefore, read command cycle cannot be ended. when to end read command cycle, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition where 'h' is input to ack signal after ar bitrary d0 and sda is started at scl signal 'h'. w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data(n) a c k slave address 10 0 1 a0 a1 a2 wa 7 a0 d0 slave address 10 0 1a1 a2 s t a r t d7 r / w r e a d wa 0 n ote ) *1 it is necessary to input 'h' to the last ack. fig.42 random read cycle (br24a01a/02/04/08/16-wm) w r i t e s t a r t r / w a c k s t o p 1st word address? sda line a c k a c k data(n) a c k slave address 1 0 0 1 a0 a1 a2 d7 d0 * 2nd word address? a c k s t a r t slave address 1 0 0 1 a2 a1 r / w r e a d a0 wa 0 note) * 1 wa 12 wa 11 ** fig.43 random read cycle (br24a32/64 -wm) *1 as for wa12, br24a32-wm become don?t care. *1 as for wa7, br24a01a-wm become don?t care. s t a r t s t o p sda line a c k data(n) a c k slave address 10 0 1 a0 a1 a2 d0 d7 r / w r e a d note) fig.44 current read cycle it is necessary to input 'h' to the last ack. r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 10 0 1 a0 a1 a2 d0 d7 d0 d7 note fig.45 sequential read cycle (in the case of current read cycle) *1 in br24a16-wm, a2 becomes p2. *2 in br24a08-wm, br24a16-wm, a1 becomes p1. *3 in br24a04-wm, a0 becomes ps, and in br24a08-wm and br24a16-wm, a0 becomes p0. 1 0 0 1a0 a1 a2 *1 *2 *3 note) fig.46 difference of slave address of each type
br24a -wm series technical note 11/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. software reset software reset is executed when to avoid malfunction after power on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the figur e below. (refer to fig.47(a), fig.47(b), and fig.47(c).) in dummy clock input area, release the sda bus ('h' by pull up). in dummy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefore, if 'h' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignor ed, therefore ack is not sent back. during internal automatic write execution after write cycle input, next command (slave addre ss) is sent, and if the first ack signal sends back 'l', then it means end of write action, while if it sends back 'h', it means now in writing. by use of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, r/w = 0, when to carry out current read cycle after write, slave address r/w = 1 is sent, and if ack signal sends back 'l', then execute word address input and data output and so forth. fig.48 case to continuously write by acknowledge polling 1 2 13 14 scl dummy clock14 start2 fig.47-(a) the case of dummy clock +start+start+ command input start command from start input. 2 1 8 9 dumm y clock9 start fig.47-(b) the case of start +9 dummy clocks +start+ command input start normal command normal command normal command normal command start9 sda 1 2 3 8 9 7 fig.47-(c) start9+ command input normal command normal command scl sda scl sda s t a r t first write command a c k h slave address slave address write command during internal write, ack = high is sent back. t wr second write command s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l slave address word address a c k l slave address data after completion of internal write, ack=low is sent back, so input next word address and data in succession. t wr s t a r t s t a r t s t o p a c k h a c k l
br24a -wm series technical note 12/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to canc el write cycle and so forth, pa y attention to the following wp valid timing. during write cycle execution, in cancel valid ar ea, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don't care. set the setup time to rise of d0 taken scl 100ns or more. the area from the rise of scl to take in d0 to the end of internal automatic write (t wr) is cancel valid area. and, when it is set wp='h' during twr, write is ended forcibly, data of address under access is not guarante ed, therefore, write it once again. (refer to fig.49.) aft er execution of forced end by wp, standby status gets in, so there is no need to wait for twr (5ms at maximum). command cancel by start condition and stop condition during command input, by continuously inputting start c ondition and stop condition, command can be cancelled. (refer to fig. 50.) however, in ack output area and during data read, sda bus ma y output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out curre nt read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. fig.49 wp valid timing fig.50 case of cancel by start, stop condition during slave address input scl sda 1 1 0 0 start condition stop condition ? rise of d0 taken clock scl d0 ack enlarged view scl sda enlarged view ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area write forced end data is not written. data not guaranteed d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address slave address
br24a -wm series technical note 13/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the consumpt ion current at action. maximum value of r pu the maximum value of r pu is determined by the following factors. (1)sda rise time to be determined by the capacitance (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda bus and rpu should sufficiently secure the input 'h' le vel (vih) of microcontroller and eeprom including recommended noise margin 0.2vcc. minimum value of r pu the minimum value of r pu is determined by the following factors. (1)when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. (2)v olmax =0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1vcc. v olmax Q v il -0.1 vcc ex. ) when vcc =3v, vol=0.4v, iol=3ma , microcontroller, eeprom vil=0.3vcc from (1) therefore, the conditi on (2) is satisfied. pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the ca se there is timing where scl becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. a0, a1, a2, wp process process of device address terminals (a0,a1,a2) check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. connect this terminal to pull up or pull down, or vcc or gnd. and, pins (n, c, pin) not used as device address may be set to any of 'h' , 'l', and 'hi-z'. types with n.c.pin br24a16/f/fj -wm a0, a1, a2 br24a08/f/fj-wm a0, a1 br24a04/f/fj -wm a0 process of wp terminal wp terminal is the terminal that prohibits and permits write in hardware manner. in 'h' status, only read is available and write of all address is prohibited. in t he case of 'l', both are available. in the case of use it as an rom, it is recommended to connect it to pull up or vcc. in the case to use both read and write, control wp terminal or connect it to pull down or gnd. r pu R 3 0.4 3 10 -3 R 867 [ ] and v ol = 0.4 [v] v il = 0.3 3 = 0.9 [v] r pu ex. ) when v cc =3v, i l =10 a, v ih =0.7 v cc , from (2) 0.8 3 - 0.7 3 10 10 -6 r pu Q Q 300 [k ? ] 0.8vcc - v ih i l vcc - i l r pu - 0.2vcc R v ih v c - v ol i ol v cc -v ol r pu Q i ol r pu Q ? r pu a br24axx sda terminal il il cbus fig.51 i/o circuit diagram microcontroller bus line capacity cbus
br24a -wm series technical note 14/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs betwe en the pull up resistance rpu an d the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sda terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. (1)sda rise time to be determined by the capacity (cbus) of bus line of rpu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by rpu and rs the moment when eeprom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1vcc. fig.54 i/o circuit diagram minimum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. fig.55 i/o circuit diagram microcontroller eeprom 'l' output r s r pu 'h' output over current v cc r s v cc i R 1010 -3 Q i r s R 300 ? example when v cc =3v, i=10ma r s R 3 example when v cc =3v, v il =0.3v cc, v ol =0.4v, r pu =20k ? , Q Q 2010 3 1.67 k ? r pu +r s (v cc v ol )r s +v ol +0.1v cc Q v il r s Q from(2), r pu v il v ol 0.1v cc 1.1v cc v il 1.13 0.33 0.33 0.4 0. 13 r s r pu microcontroller r s fig.52 i/o circuit diagram fig.53 input / output collision timing eeprom 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda r pu microcontroller r s eeprom i ol a bus line capacity cbus v ol v cc v il
br24a -wm series technical note 15/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. i 2 c bus input / output circuit input (a0,a2,scl) input / output (sda) input (a1, wp) notes on power on at power on, in ic internal circuit and set, vcc rises through uns table low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent this, functions of po r circuit and lvcc circuit are equipped. to assure the action, observe the following conditions at power on. 1. set sda = 'h' and scl ='l' or 'h' 2. start power source so as to satisfy the recommended conditions of t r , t off , and vbot for operating por circuit. recommended conditions of t r , t off ,vbot t r t off vbot 10ms or below 10ms or longer 0.3v or below 100ms or below 10ms or longer 0.2v or below fig.56 input pin circuit diagram fig.57 input / output pin circuit diagram fig.58 input pin circuit diagram t off t r vbot 0 v cc fig.59 rise waveform diagram
br24a -wm series technical note 16/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(p11). c) in the case when the above c onditions 1 and 2 cannot be observed. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and prev ents wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. vcc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfun ction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1 f) between ic vcc and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. note of use (1) described numeric values and data are design repres entative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your deci sion with sufficient margin in consideration of static characterist ics and transition characteristics and fluc tuations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed volt age and action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperat ure exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4)gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that each terminal voltage is lower than that of gnd terminal. (5)terminal design in consideration of permissible loss in actual use cond ition, carry out heat design with sufficient margin. (6)terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay sufficient attent ion to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause ma lfunction, therefore, eval uate design sufficiently. t low t su:dat t dh a fter vcc becomes stable scl v cc sda after vcc becomes stable t su:dat fig.60 when scl= 'h' and sda= 'l' fig.61 when scl='l' and sda='l'
br24a -wm series technical note 17/17 www.rohm.com 2009.08 - rev.c ? 2009 rohm co., ltd. all rights reserved. ordering part number b r 2 4 a 0 1 f - w m e 2 part no. bus type operating capacity package double cell packaging and forming specification 24 :i 2 c temperature 01= 1k 02= 2k f : sop8 e2: embossed tape and reel a:-40 04= 4k 08= 8k fj : sop-j8 tr: embossed tape and reel +105 16=16k 32=32k fvm : msop8 64=64k package specifications (unit : mm) sop8 0.9 0.15 0.3min 4 + 6 ? 4 0.17 +0.1 - 0.05 0.595 6 4 3 8 2 5 1 7 5.0 0.2 6.2 0.3 4.4 0.2 (max 5.35 include burr) 1.27 0.11 0.42 0.1 1.5 0.1 s ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin (unit : mm) sop-j8 4 + 6 ? 4 0.2 0.1 0.45min 234 5 6 7 8 1 4.9 0.2 0.545 3.9 0.2 6.0 0.3 (max 5.25 include burr) 0.42 0.1 1.27 0.175 1.375 0.1 0.1 s s (unit : mm) msop8 0.08 s s 4.0 0.2 8 3 2.8 0.1 1 6 2.9 0.1 0.475 4 5 7 (max 3.25 include burr) 2 1pin mark 0.9max 0.75 0.05 0.65 0.08 0.05 0.22 +0.05 ?0.04 0.6 0.2 0.29 0.15 0.145 +0.05 ?0.03 4 + 6 ? 4 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs tr () 1pin
r0039 a www.rohm.com ? 2009 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redundancy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

▲Up To Search▲

Price & Availability of BR24A01AFJ-WM

	To Download BR24A01AFJ-WM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .